Comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards
Silicon Library (SLI) DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4b TX IP cores provide a comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards, enabling seamless integration into SoCs for modern multimedia applications. The solution consists of two modules: a physical layer (PHY) and a controller (Link Layer / PCS). The PHY is a hard macro supporting high-speed data rates up to 8.1Gbps (HBR3), while the controller is provided as a synthesizable soft macro. In addition to required DisplayPort functionalities, the solution supports optional features including Multi-Stream Transport (MST), Display Stream Compression (DSC), Forward Error Correction (FEC) and HDCP 1.4/2.3 Content Protections by its configurable controller. SLI’s PHY IPs and Controller IPs work together to deliver the best results with simplified integration although SLI’s PHY and Controller IPs can be offered as independent products .
This PHY IP is available as Silicon proven ‘off-the-shelf’ IP in various major fabs and technology nodes from 12nm to 55nm.
PHY Features
Controller Features
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DisplayPort 1.4a / eDP 1.4b TX PHY and Controller IP is a Displayport IP core from Silicon Library Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.
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