Vendor: Silicon Library Inc. Category: Displayport

DisplayPort 1.4a / eDP 1.4b TX PHY and Controller IP

Comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards

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Overview

Silicon Library (SLI) DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4b TX IP cores provide a comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards, enabling seamless integration into SoCs for modern multimedia applications. The solution consists of two modules: a physical layer (PHY) and a controller (Link Layer / PCS). The PHY is a hard macro supporting high-speed data rates up to 8.1Gbps (HBR3), while the controller is provided as a synthesizable soft macro. In addition to required DisplayPort functionalities, the solution supports optional features including Multi-Stream Transport (MST), Display Stream Compression (DSC), Forward Error Correction (FEC) and HDCP 1.4/2.3 Content Protections by its configurable controller. SLI’s PHY IPs and Controller IPs work together to deliver the best results with simplified integration although SLI’s PHY and Controller IPs can be offered as independent products .

This PHY IP is available as Silicon proven ‘off-the-shelf’ IP in various major fabs and technology nodes from 12nm to 55nm.

Key features

PHY Features

  • DP version 1.4a / eDP version 1.4b compliant transmitter
  • Supports both SST and MST (up to 4 streams) modes
  • Configurable (4/2/1) link channels and one AUX channel
  • 1.62Gbps (RBR), 2.7Gbps (HBR), 5.4Gbps (HBR2), and 8.1Gbps (HBR3) per lane
    •  Also supports all recommended data rates (i.e. 2.16Gbps) defined in eDP v1.4b
  • Programable pre-emphasis
  • Programable analog characteristics
  • Test modes including Loopback test, PLL test and DC test

Controller Features

  • DP version 1.4a / eDP version 1.4b compliant transmitter
  • Supports SST and optionally MST (up to 4 streams) modes
  • Supports both video packet and audio packet
    • Supports all digital video output formats (RGB/YCbCr/RAW/Y-only)
    • Supports LPCM audio (up to 8ch) via I2S slave I/F
  • Supports both Default and Enhanced Framing Modes
  • Hardware link training management
  • Hardware EDID reading via AUX CH
  • Configuration registers programmable via AMBA APB interface
  • Supports HDCP 1.4 / 2.3 (optional)
  • Supports DSC and FEC (Rambus Inc) as options

Block Diagram

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Specifications

Identity

Part Number
DisplayPort 1.4a / eDP 1.4b TX PHY and Controller IP
Vendor
Silicon Library Inc.
Type
Silicon IP
Controller / PHY
Controller , PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Displayport IP core

Silicon Library: Notice of Stock Transfer

We are pleased to inform you that we have decided to transfer the shares of our company. We would like to take this opportunity to thank you for your continued support.

Silicon Library Inc. develops SD UHS-II PHY MACRO

Silicon Library Inc. develops SD UHS-II PHY Macro. SLI ZRSLSIPSDUHS2PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC

Frequently asked questions about DisplayPort IP cores

What is DisplayPort 1.4a / eDP 1.4b TX PHY and Controller IP?

DisplayPort 1.4a / eDP 1.4b TX PHY and Controller IP is a Displayport IP core from Silicon Library Inc. listed on Semi IP Hub.

How should engineers evaluate this Displayport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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