Vendor: Naneng Microelectronics Category: V-By-One

V-By-One HS Receiver PHY

Key features

  • Next generation HD interface with low EMI
  • Fully comply with V-By-One HS V1.3 electrical specification
  • Low power consumption for multiple lane application
  • Compact size: 0.1mm2 per lane including PMU and IO PAD
  • Support Data rate: 0.6Gbps~4Gbps per lane
  • 9bit/10bit parallel interface
  • Implemented CTLE to compensate channel loss
  • Integrated on-die termination resistors
  • Tolerance frequency offset up ±15000ppm
  • Build-in self-test facility
  • AC coupling
  • Support up to x16 lanes
  • Support BGA, QFN/QFP package
  • ESD performance: HBM >6000V / IEC >6000V

Applications

  • TV / Display / Monitor
  • Automotive / Medical appliance
  • Multimedia / Amusement Devices
  • Cameras
  • Multifunction printers / projectors

Specifications

Identity

Part Number
V-By-One HS Receiver PHY
Vendor
Naneng Microelectronics
Type
Silicon IP

Files

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Provider

Learn more about V-By-One IP core

The Benefits of a Multi-Protocol PMA

At Silicon Creations, we have developed a power and area optimized, flexible and programmable PMA (Physical Medium Attachment) architecture that can be reliably ported to different process nodes and scaled across protocol generations as data rates increase. It is called the Multi-Protocol PMA, or MP-PMA for short.

Frequently asked questions about V-by-One IP cores

What is V-By-One HS Receiver PHY?

V-By-One HS Receiver PHY is a V-By-One IP core from Naneng Microelectronics listed on Semi IP Hub.

How should engineers evaluate this V-By-One?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this V-By-One IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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