DSC Decoder
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
Overview
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
Key features
- Compliant with VESA DSC 1.2b, backward compatible with DSC 1.1
- Supports all mandatory and optional coding schemes:
- Modified Median-Adaptive Prediction (MMAP)
- Midpoint Prediction (MPP)
- Block Prediction (BP)
- Indexed Color History (ICH)
- Compatible with MIPI DSI-2 v1.1, DisplayPort 1.4, and HDMI 2.1
- Real-time, visually lossless encoding and decoding for high-bandwidth displays
- Configurable maximum resolution and up to 4 slices per line
- Operates within a single clock domain to avoid CDC (Clock Domain Crossing) issues
- Supports 8 / 10 / 12-bit per video component
- Color formats: YCbCr 4:4:4, 4:2:2, 4:2:0 and RGB 4:4:4
- Processing performance:
- 3 pixels/clock for 4:4:4
- 6 pixels/clock for 4:2:2 and 4:2:0
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about VESA DSC IP cores
What is DSC Decoder?
DSC Decoder is a VESA DSC IP core from Qualitas Semiconductor listed on Semi IP Hub.
How should engineers evaluate this VESA DSC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this VESA DSC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.