The Xilinx® HDMI solutions include HDMI TX and RX subsystems.
- HDMI
Multimedia Interface IP cores provide the high-speed connectivity technologies required to transport video, audio, image, and display data across modern SoCs, ASICs, and electronic systems. These interfaces are essential for enabling seamless communication between processors, cameras, displays, sensors, and multimedia subsystems.
This category includes HDMI, DisplayPort, MIPI, V-By-One, and VESA DSC (Display Stream Compression) IP solutions. Available implementations may include controllers, PHYs, protocol stacks, bridge solutions, and complete subsystem IP supporting high-resolution displays, camera interfaces, video transport, display compression, and multimedia data exchange.
Compare multimedia interface IP cores by protocol standard, feature set, implementation model, and vendor offering to support your video, display, and media connectivity roadmap.
The Xilinx® HDMI solutions include HDMI TX and RX subsystems.
MIPI CSI-2 RX Controller Subsystem
The Xilinx MIPI CSI2 Receiver Subsystem implements the Mobile Industry Processor Interface (MIPI) based Camera Serial Interface (…
DisplayPort and HDMI Transmit technologies are complex mixed signal designs which require both high performance analog design (eq…
The DisplayPort Transmistter IP core is fully compliant with DisplayPort 1.1a with HDCP content protection specifications.
The Xilinx DisplayPort® solutions include DisplayPort LogiCORE™ and DisplayPort TX and RX subsystems.
HDMI 1.4 transmitter IP core is ideal for DVD, Blu-Ray Disc players, set-top boxes, A/V receivers
Analogix offers its silicon-proven HDMI IP cores (digital plus analogix PHY) for integration into customer's system-on-chip produ…
LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
V-Trans 's LVDS Display interface IP is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allo…
MIPI RX controller on SMIC 28nm
MIPI RX controller is a mass production IP in SMIC 28nm supported MIPI DSI & DCS protocols.
DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a.
HDCP 1.4/2.2/2.3 for DisplayPort
HDCP 1.4/2.2/2.3 for DisplayPort
450 Mbit/s - 2 Gbit/s Display Transmitter
IP
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.
MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process
MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process
eDP (Embedded Displayport) receiver Link/PCS IP core is compliant with eDP 1.4a/DP 1.3 specification.
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer ra…
V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller).
V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller).
V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller).
V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller).
Analog part of 600Mbps to 4Gbps 4-lane V-By-One receiver with embedded CDR circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.
MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI Transmitter Controller.