Vendor: Parretto Category: Displayport

DisplayPort 1.4 IP-core

This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX).

Overview

This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX).

The solution comes also with a Video Toolbox (VTB) for various video processing tasks including a timing generator, a test pattern generator and video clock recovery.

​A thin host driver and API allow easy integration and control of the IP-core.

​The IP-core is supported by a wide range of FPGA devices including; 

  • AMD UltraScale+
  • AMD Artix-7
  • Intel Cyclone 10 GX
  • Intel Arria 10 GX
  • Lattice CertusPro-NX

The IP-core source code is available on our GitHub page for your convenience. You can customize and tailor the IP-core to your specific needs and requirements, ensuring that it integrates seamlessly with your system. This also adds trust to your product, knowing that you have complete access to the underlying code.

​The documentation provides detailed information on the features, configuration and reference design.

Key features

  • Support for 1.62, 2.7, 5.4, and 8.1 Gbps link rates (including eDP rates)
  • Support for 1, 2, and 4 DP lanes
  • Native video and AXI stream video interfaces 
  • Single Stream transport mode (SST)
  • Multi Stream transport mode (MST)
  • Dual and quad pixels per clock
  • 8 & 10-bits video
  • RGB 4:4:4 & YUV 4:4:4 colorspaces
  • Secondary data packet interface for audio and meta data transport

Specifications

Identity

Part Number
PRT-DP
Vendor
Parretto
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: The Netherlands

Learn more about Displayport IP core

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DisplayPort 2025: Navigating the Next Wave of Display Innovation

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Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about DisplayPort IP cores

What is DisplayPort 1.4 IP-core?

DisplayPort 1.4 IP-core is a Displayport IP core from Parretto listed on Semi IP Hub.

How should engineers evaluate this Displayport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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