PHY / Serdes IP Cores for TSMC

C-PHY/D-PHY Combo in numerous process nodes at low cost and power.

• MIPI D-PHY
• TSMC
• 22nm
• ULP
• In Production

In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

Low power and cost C-PHY/D-PHY Combo in multiple process nodes.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

C-PHY/D-PHY Combo in various process nodes with low power and cost.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

The D-PHY specification, version 1.2, is fully complied with by the MIPI D-PHY Analog RX IP Core.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

C-PHY/D-PHY Combo in various process nodes with low power and cost.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

Various manufacturing nodes using C-PHY/D-PHY Combo at minimal cost and power.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.

• USB 2.0
• TSMC
• 90nm
• G
• In Production

A physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.

• USB 2.0
• TSMC
• 65nm
• LP
• In Production

In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed.

• USB 2.0
• TSMC
• 55nm
• LP
• In Production

The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption.

• USB 2.0
• TSMC
• 12nm
• FFC
• In Production

The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.

• USB 2.0
• TSMC
• 7nm
• N7FF
• In Production

For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.

• USB 3.0
• TSMC
• 55nm
• LP
• In Production