Camera MIPI D-PHY Receiver 4.5Gbps 4-Lane

The CL12632M4R1AS1BIP4500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12632M4R1AS1BIP4500 is designed to support data rate in excess of maximum 4.5Gbps utilizing MIPI D-PHY v2-1 interface specification.

• MIPI D-PHY v2-1 / MIPI CSI2 compliant
• Supporting for four kind Differential Input Signals: MIPI D-PHY (Maximum 4.5Gbps)
• Maximum Input Clock Frequency: ~2.25GHz ,
• Maximum Input Data Transfer Rate: ~4.5Gbps
• Power Supply : Vcc=1.8V (IO and Analog) Vdd=0.9 V (Inside Core)
• Maximum Lane Number : 4-Lane
• 8-bit/Lane Parallel Outputs
• Including Power Down Mode
• TSMC 28nm HPC+ Process
• Poly Direction: South-North
• Various process porting support available ( Please contact us. )
• Supporting Link-layer: CD12632IP soft macro

• This IP is supported almost CMOS Image Sensor. Thus if when the customer want to use customer's LSI other system set, the customer don't need to change IP, because this IP can change Interface type to same PAD for changing mode pin.
• The system customer can select from many CMOS image sensor for using out IP.
• We are updating CMOS Image Sensor's modelnumber of verify operation for getting information from customer and ourself at all time.
• If the customer need combo Link-layer, we can provide them and can support system.
• We are provided CIS and TX Verilog Model. Thus the customer can confirm function by verilog simulation status.

• Camera Application
  • Security Camera
  • Mobile-Phone Camera
  • DSC(Digital Still Camera)
  • Medical Camera
  • SLR
  • 3D Camera
  • Camcorder
• ISP(Image Signal Processer)

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Link Layer IP(CD12632IP) and FPGA Board(Option)