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Vendor:
Synopsys, Inc.
Category:
Single-Protocol PHY
224G Ethernet PHY for TSMC 3nm
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth…
Overview
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the Synopsys 224G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications. The area efficient PHY provides additional margin for channel loss and demonstrates zero post-FEC BER.
The PHY supports the Pulse-Amplitude Modulation 4 (PAM-4) and Non- Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet. The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The Continuous Calibration and Adaptation (CCA) algorithm provides robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.
The PHY has been co-designed and optimized with the Synopsys Physical Coding Sublayer (PCS) and Media Access Controller (MAC) IP to reduce integration time and provide solution level differentiation.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 224G Ethernet PHY solution for fast and reliable SoC integration and first pass silicon success.
The PHY supports the Pulse-Amplitude Modulation 4 (PAM-4) and Non- Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet. The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The Continuous Calibration and Adaptation (CCA) algorithm provides robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.
The PHY has been co-designed and optimized with the Synopsys Physical Coding Sublayer (PCS) and Media Access Controller (MAC) IP to reduce integration time and provide solution level differentiation.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 224G Ethernet PHY solution for fast and reliable SoC integration and first pass silicon success.
Key features
- Supports full-duplex 1.25 to 224Gbps data rates
- Enables 200G, 400G, 800G, and 1.6T Ethernet
- Ethernet interconnects for wired network infrastructure
- Supports IEEE 802.3 and OIF-224G standards electrical specifications
- Meets the performance requirements of chip-to-chip, chip-to-module, and long reach copper/ backplane interconnects
- DAC-based PAM-4 transmitter includes feed-forward equalization (FFE)
- Digital-based receiver consists of analog front-end (AFE), ADC, and advanced digital signal processor (DSP)
- High-performance receiver equalization supports channel loss of 45dB
- Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature
- Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
Benefits
- Optimized for performance, power, latency, and area
- Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
- Supports IEEE and OIF-CEI-224G standards
- Includes auto-negotiation and link training capabilities
- Low jitter transmitter and receiver (dual loop clock and data recovery) clock architectures
- Multi-lane PHY shares a single clock and support core
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and advanced DSP-based receiver with analog-to-digital converter
- Optimal receiver jitter tolerance supports a wider range of board layout designs and immunity to interference (cross talk), and reduces design constraints on board signal paths
- Contains embedded pseudo random bit sequence (PRBS) for internal and external loopbacks
- Embedded bit error rate (BER) tester and non-destructive internal eye monitor
Applications
- Hyperscale data center
- Enterprise and campus networks
- High-performance computing/networking
- Service provider networks
- Artificial intelligence and machine learning
What’s Included?
- Verilog models and test bench; Protocol-specific test bench; Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl); GDSII; IP-XACT XML files with register details; ATPG models; IBIS-AMI models; Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 3nm | N3A | — |
Specifications
Identity
Part Number
dwc_224g_ethernet_phy_tsmc3nm
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is 224G Ethernet PHY for TSMC 3nm?
224G Ethernet PHY for TSMC 3nm is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.