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Vendor:
Synopsys, Inc.
Category:
Single-Protocol PHY
56G Ethernet PHY in TSMC (16nm, 12nm)
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…
Overview
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification IP, is designed to meet all required features of the PCI Express® (PCIe®) 6.0, 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications. By providing a complete IP solution, Synopsys delivers
optimization across the individual IP to lower latency and ensures that all the IP functions seamlessly together to lower integration risk. The high-performance PCI Express IP solution is optimized for low power, small area and low latency.
The high-quality IP solution has been extensively validated with multiple hardware platforms, PHYs, and PCIe verification suites across a broad range of processes and foundries. With thousands of design wins and products shipping in volume, Synopsys’ expertise in developing and supporting the PCI Express interface enables designers to accelerate time-to-market and achieve silicon success for their advanced SoCs.
optimization across the individual IP to lower latency and ensures that all the IP functions seamlessly together to lower integration risk. The high-performance PCI Express IP solution is optimized for low power, small area and low latency.
The high-quality IP solution has been extensively validated with multiple hardware platforms, PHYs, and PCIe verification suites across a broad range of processes and foundries. With thousands of design wins and products shipping in volume, Synopsys’ expertise in developing and supporting the PCI Express interface enables designers to accelerate time-to-market and achieve silicon success for their advanced SoCs.
Key features
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver
- Optimized High performance analog front-end with adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE) for PCIe 5.0 and ADC/DSP based architecture for PCIe 6.0
- Continuous calibration and adaptation (CCA) for a robust performance across voltage and temperature variations
- Spread-spectrum clocking (SSC) and PCIe Separate Refclk Independent SSC (SSIS)
- Supports PCIe power management features, including L0p, L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
- The multi-channel PHY macro with single clock and control core for higher density with support for both internal and external reference clock inputs
- PIPE bifurcation as well as PHY macro aggregation for x1 to x16 PHY configurations
- Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
- Automated Test Equipment (ATE) test vectors for complete at-speed production testing
- Each PHY channel contains its own 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks
- Each channel is fully controllable via the integrated logic core as well as the test access port (TAP)
- Support for various form-factors
Benefits
- Designed to meet all required features of the PCI Express 6.0 (64 GT/s), 5.0 (32GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s) and 1.1 (2.5 GT/s), and PIPE specifications
- Comprehensive suite of configurable controllers for Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode, and Multi-Port Switch applications
- Optimized for low power, small area and low latency
- PHYs include advanced built-in diagnostics, enabling at-speed production testing on low-cost digital tester
- Automotive Safety Integrity Level (ASIL) B Ready ISO 26262 certified controller and PHY IP
- Built-in applications in the verification IP accelerate testbench development
- Standards-compliant Synopsys Integrity and Data Encryption Security Modules protect data transfer and are pre-verified with Synopsys Controller IP for PCI Express for fast integration and low risk
Applications
- Enterprise computing, storage area networks, networking switches, and routers
- Wireless and mobile devices
- Industrial, automotive, and IoT
- Embedded systems and set-top boxes
- Graphics devices
- Desktops, laptops, workstations, and servers
What’s Included?
- Verilog models
- Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
- GDSII
- IP-XACT XML files with register details
- ATPG models; IBIS-AMI models
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 6nm | N6FF | Available on request |
Specifications
Identity
Part Number
dwc_56g_ethernet_phy_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP
Videos
7-nm DesignWare 56G Ethernet PHY IP Performance Results
This video shows the performance and capabilities of Synopsys’ DesignWare 56G Ethernet PHY IP in 7-nm FinFET process. The jitter performance of the transmitter and receiver exceed electrical specifications. The IP is designed to meet the needs of today’s 400G hyperscale data center SoCs.
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is 56G Ethernet PHY in TSMC (16nm, 12nm)?
56G Ethernet PHY in TSMC (16nm, 12nm) is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.