Overview
PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP. With compatibility for PIPE 4.3 interface spec, this complies with PCIe Rev3 Base Specification. 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, all three are supported by the output data rate (serial), which has a 25Mhz input clock frequency. 2.5, 5, and 8 gigabits per second. A minimum of 10 Pads and a maximum clock speed of 500MHz are needed. Range of operating voltages: - 2.97V-3.63V, typical =3.3V; 0.99V-1.21V, usual = 1.1V;
Learn more about Multi-Protocol PHY IP core
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
Steven Brown
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
