IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
T2M GmbH
Category:
MIPI PHY
MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification.
Overview
The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification. It supports both the MIPI Camera Serial Interface (CSI-2) and the Display Serial Interface (DSI) protocols. This TX PHY comprises one clock lane and four data lanes. The D-PHY integrates an analog front end responsible for generating and receiving electrical level signals, along with a digital back end controlling the I/O functions. Additionally, it features an internal termination resistor with auto-calibration. This MIPI DSI PHY (MIPI TX DPHY) includes a PLL, a Clock Lane, and four Data Lanes for MIPI DSI data transmission. Moreover, the D-PHY can function as a 5V tolerance GPIO bank.
Key features
- DSI PCS :
- The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.
- Host_adapter: remapping PPI Signal with lane control and phy_adapter block;
- Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)
- acknowledges the operation on PPI interface. It enables a high-speed transmission or low-power transmission/reception and schedules the activities inside the link.
- PHY_adapter: remappig lane_ctrl Signal with phy interface;
- DSI PMA:
- A PLL for high speed clock and MIPI data clock generation
- Data MUX and Reference resistor calibration
- MIPI PHY IO with GPIO compatible
- Silicon Proven in TSMC 22ULP
Block Diagram
MIPI D-PHY Tx IP in 22ULP block diagram
Benefits
- DSI PCS :
- The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.
- Host_adapter: remappig PPI Signal with lane control and phy_adapter block;
- Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)
- acknowledges the operation on PPI interface. It enables a high-speed transmission or low-power transmission/reception and schedules the activities inside the link.
- PHY_adapter: remappig lane_ctrl Signal with phy interface;
- DSI PMA:
- A PLL for high speed clock and MIPI data clock generation
- Data MUX and Reference resistor calibration
- MIPI PHY IO with GPIO compatible
Applications
- Automotive
- Mobile
- IoT
- Consumer Electronics
- VR
- AR
What’s Included?
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 22nm | ULP | In Production |
Specifications
Identity
Part Number
MIPI D-PHY Tx IP in 22ULP
Vendor
T2M GmbH
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI D-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
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Frequently asked questions about MIPI PHY IP
What is MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP?
MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP is a MIPI PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.