Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
- Channel Coding
- Now
- 3GPP TS 25.212 V5.2.0 Relea…
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
8-Channel PCM-to-PWM Modulator in Fujitsu 55nm
The AR35F01A is a digitally coded conversion IP that translates 8-ch (4 stereo channels) of 16-24bit pulse-code modulated (PCM) i…
This design is a DVB-T2 OFDM demodulator, supplied as portable and synthesizable Verilog-2001 IP.
High Throughput and Low Latency Compression Engine For SSD
The high performance compression IPhere compresses at the line rate of 16Gbps in ASIC or up to 64 Gbps for custom implementations.
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
MicroBlaze™ is the Xilinx® 32-bit RISC Harvard architecture soft processor core with a rich instruction set optimized for embedde…
High-performance Processor for Real-time and Linux Applications
The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running eith…
High-efficiency Low-power Processor
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door…
Entry-level Low-Power 32-bit Processor
N705 is an ultra low-power small-size synthesizable general purpose 32-bit softcore embedded processor.
The D68HC11F is a synthesisable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard.
8-bit Microcontroller IP - legacy architecture - raplacement of 68HC11K MCU's
The D68HC11K is synthesisable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard.
The D6803 is synthesisable, SOFT Microcontroller IP Core, fully compatible with the Motorola MC6803.
The eSi-QRD-LSL is a QR-Decomposition Least Squares Lattice (QRD-LSL) core is a high throughput IP core that finds application in…
Continuously Variable Slope Delta Modulation
The growth in wireless communication systems, cellular mobile radio and VoIP technology has created the imperative need for bandw…
Beyond BA21 implements a 32-bit low-power processor that delivers better performance than most processors of its size.
A efficient pipelined radix-2 squared FFT.
Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.