Scalable and Programmable Co-processor
Simpulse’s Pulsar DSP IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital s…
- DSP Core
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Scalable and Programmable Co-processor
Simpulse’s Pulsar DSP IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital s…
ITU-T G729A Voice Codec Hardware Accelerator
The growth in wireless communication systems, cellular mobile radio and VoIP technology has created the imperative need for bandw…
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream.
16/32-bit Microprocessor with BDM
The D68000-BDM soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor.
Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to D…
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…
Digital signal processing has been widely used in the area of sensor devices, smart meter, biometrics, communication, Audio, spee…
Highly-Configurable 32-bit Processor
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including …
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
The MVD ATSC core is a drop-in module for FPGA that includes the following functions: - Input data framer from DVB-SPI source (MP…
The block consists of 4 low pass filters connected in serially.
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer.
Maximum normalised correlation core
The eSi-MNC core provides the control and data plane interfaces to a Maximum Normalised Correlation module.
Nand Flash write cycles are limited.
So_ip_idt core can be used create a decision tree directly in hardware.
8051 Compatible Microcontroller Core
The so_ip_8051M256 is a soft core of a single-chip 8-bit embedded microcontroller dedicated for operation with fast (on-chip) and…
The so_ip_8051C256 is a soft core of a 8-bit CPU dedicated for operation with fast (on-chip) and slow (off-chip) memories.
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator.
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3a…