Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
High-efficiency Low-power Processor
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door…
Overview
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door locks, smoke, fire, and intrusion detection and more. SoC designers building chips for these applications need a feature rich 32-bit computing platform that provides a roadmap to enhanced functionality over time. The AndesCore™ N8 with its 3-stage pipeline design boosts the execution efficiency of today's computation algorithms, reduces memory usage, lowers customers' silicon cost, while providing a long-term roadmap for customers needing an upgrade path from 8-bit cores.
Motion, magnetic, pressure, light and temperature sensors are at the heart of IoT devices for home automation. Embedded processors to control these sensors and communicate their readings to the web must be power efficient enough to run on batteries sometimes last more than 10 years, for example the intrusion sensors on door and windows. The N8 achieves 1.82 DMIPS/MHz, which are far more computing power and energy conservation than its peers.
Motion, magnetic, pressure, light and temperature sensors are at the heart of IoT devices for home automation. Embedded processors to control these sensors and communicate their readings to the web must be power efficient enough to run on batteries sometimes last more than 10 years, for example the intrusion sensors on door and windows. The N8 achieves 1.82 DMIPS/MHz, which are far more computing power and energy conservation than its peers.
Key features
- Excellent total performance deliverable
- Vectored interrupt for low latency interrupt processing
- Small footprint with low gate count and high code density
- Speed-up and power reduction for Flash accesses by FlashFetch technology
Block Diagram
AndesCore ™ N820 block diagram
Benefits
- Performance
- 16/32bit mixable instruction format for compacting code density
- Branch predication to speed up loop control
- Low-latency vectored interrupt for real-time performance
- FlashFetch technology to accelerate internal parallel and/or external
- SPI flash memory
- Advanced CoDense™ technology to reduce program code size
- Flexibility
- All-C Embedded Programming
- Stack protection hardware to help determining stack size needed,
- and detect runtime overflow error
- Support boot-up from instruction Local Memory
- Processor state bus to simplify SoC design and debugging
- Power Management
- Low power modes initiated by SW or SoC
- PowerBrake technology to digitally reduce peak power consumption
Applications
- Internet of Things (IOT)
- Sensor hub
- Smart thermostat controller
- Home security/automation controller
- Smart Gas/Water/Electronic meter
- Personal health device
- Wearable device
- PC/Notebook peripheral
Specifications
Identity
Part Number
AndesCore ™ N820
Vendor
Andes Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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Frequently asked questions about CPU IP cores
What is High-efficiency Low-power Processor?
High-efficiency Low-power Processor is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.