In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
- Channel Coding
- Mature
- Now
- 3GPP LTE
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
TC5100 is a flexible LDPC encoder/decoder Core.
The Arm® Cortex®-A55 is the most power efficient mid-range application CPU built on Arm DynamIQ technology.
64-bit embedded processor, fully compliant with the RISC-V ISA
SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
Noesis Technologies ntSYNC is a fully programmable component used to achieve time and frequency synchronization in OFDM technolog…
DVB S2/S Satellite Tuner SoC White Box IP
This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting.
SPC (Synthesizable Programmable Core) is a soft FPGA core that is fully integrated into standard design flows and that allows the…
The MVD ISDB-T core is a drop-in module that includes the following functions : • Input data framer from DVB-SPI source (MPEG-TS …
Scalable & Royalty-Free 32-bit CPU
The D32PRO is a royalty free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floati…
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
The DVB-T2 core allows the transmission of an MPEG-TS data stream to a digital to analog converter in base band, IF or RF mode.
Super-Fast, Configurable 16-bit 80251 Microcontroller Core
The S80251XC3 core implements a high-performance 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and i…
Small, ultra-low-power, and very processing-efficient 32-bit processor
The Beyond BA20 PipelineZero Embedded Processor implements a small, ultra-low-power, and very processing-efficient 32-bit process…
2.5 Gb/s Digital RF Up Converter for AD9739A
The MVD Upconverter core is a drop-in module that converts multiple baseband I-Q signals to analog RF signal with AD9739 or AD973…
The DZ80 is an , 8-bit microprocessor, with 208 bits of user-accessible registers.
The LCD01G is a fully compatible GEO Mobile Radio (GMR-1) LDPC error control decoder.