High-performance Processor for Real-time and Linux Applications

The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating systems or as bare metal. The N13 is designed to serve the demanding requirements of application processors in SoCs for consumer electronics such as HDTVs, home media servers, cable and over-the-top set top boxes, as well as SoCs for the switches and routers delivering content to these devices.

Complete with Memory Management Unit, L1/L2 cache, Local Memory, DMA, FPU, Vectored Interrupt, and Branch Prediction, the N13 easily runs complex operating system such as Linux. And with an 8-stage pipeline and a clock rate over 1 GHz, the core delivers impressive performance of 2.05 DMIPS/MHz to serve the most demanding computing environments. Furthermore, the N13 AndesCore™ supports the latest AndeStar™ V3 architecture, which is accompanied with toolchain, IDE, RTOS, Linux, middleware, and platform development IP. The N13's strength plus its ecosystem provide designers with the competitive edge for success in their embedded system solutions.

• Optimized pipeline for best performance with over 1 GHz
• Dynamic branch prediction accelerates loop execution
• Unified Local Memory (ULM) for simultaneous accesses
• 64-bit AXI bus for high bandwidth and low latency
• MMU and MPU for Linux and RTOS
• Support for FPU coprocessor and L2 cache

• Performance
  • Highly compact program size through AndeStar™ V3 ISA
  • Optional saturation instructions for efficient voice applications
  • Single-cycle latency for most of 32-bit operations
  • Extensive branch predictions to speed up branch control
  • Efficient atomic access synchronization without locking system bus
  • Low latency vectored interrupt improving real-time performance
  • Single-cycle local memory interface with adjustable wait cycles
  • Optional 2D Local Memory DMA for efficient data transfers
  • Optional 64-bit datapath between bus and caches with power reduction architecture
  • Optional HW page table walker for MMU
  • Processor state bus to simplify SoC design and debugging
• Flexibility
  • Easy arrangement of preemptive interrupts
  • Memory-mapped IO space
  • All-C Embedded Programming
  • Stack protection hardware to help determining stack size needed, and detect runtime overflow error
  • PC-relative jumps for position independent code
  • JTAG-based debug support
  • Performance monitors
  • Support for bi-endian data accesses
  • Support boot-up from AXI if both AHB and AXI exists
  • Optional unified local memory interface for flexible code and data location
• Power Management
  • Highly clock gating and logic gating
  • Standby instructions to help power management
  • N:1 core vs bus clock ratios
  • PowerBrake technology to reduce peak power consumption

• Networking device
• WiFi device
• GPON
• Surveillance system
• ADAS
• Storage device
• Digital TV/Set top box
• Media center