LTE/NR Small Block Lengths Decoder
TC5390 is a decoder IP Core compliant with the small block lengths coding scheme for UCI as defined by 3GPP 4G-LTE and 5G-NR spec…
- Channel Coding
- proven
- now
- 3GPP 5G
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
LTE/NR Small Block Lengths Decoder
TC5390 is a decoder IP Core compliant with the small block lengths coding scheme for UCI as defined by 3GPP 4G-LTE and 5G-NR spec…
DVB-T2 Demodulator and LDPC/ BCH Decoder
The demodulator is designed to be used together with an RF tuner, and an analog to digital converter.
The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code…
CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K
The IPrium-LDPC-CCSDS-AR4JA-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm…
IEEE 802.11n/ac/ax Encoder and Decoder
The IPrium-LDPC-802.11-WIFI-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm…
The LCE02C is a high speed encoder for the CCSDS telemetry (TM) accumulate, repeat by four, jagged accumulate (AR4JA) low density…
CCSDS Rate 1/2 TC and TM LDPC Decoder
The LCD03C is a low complexity decoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC)…
CCSDS Rate 1/2 TC and TM LDPC Encoder
The LCE03C is a low complexity encoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC)…
DVB-RCS2 Turbo Decoder and Encoder
On the transmitter side, the turbo-phi encoder architecture is based on a parallel concatenation of two double-binary Recursive S…
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
The LDPC Error Correction Core (Alcyone) delivers industry- error correction performance to enable 2D/3D, SLC/MLC/TLC/QLC NAND Fl…
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser a…
CCSDS turbo decoder with sync marker synchroniser, descrambler and input memory
This is a CCSDS compatible 16 state error control turbo decoder with optional synchronisation, optional descrambling and input me…
DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder
The LCD01D is a high speed decoder for the DVB-S2/DVB-S2X low density parity check (LDPC) and Bose, Chaudhuri and Hocquenghem (BC…
The Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…