The BCH decoder has four main functional blocks along with memory blocks.
- Channel Coding
- In Production
- Immediate
- yes
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
The BCH decoder has four main functional blocks along with memory blocks.
DVB-S2X-LDPC Decoder
LDPC codec for NAND FLASH error correction
The LDPC IP is aLow-densityparity-check code encoder and decoder designed for 3D NAND Flash error correction to address the relia…
16 state DVB-RCS2 Turbo Encoder
This is a 16 state DVB-RCS2 compatible parallel concatenated turbo encoder.
TC5300 is an efficient Polar encoder/decoder Core solution compliant with 3GPP NR (5G) specifications.
TC5200 is an efficient LDPC encoder/decoder Core solution fully compliant with 3GPP NR (5G) specifications.
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15
Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15.
16 State DVB-S2/DVB-S2X Tail Biting Viterbi Decoder
The VA04D is a 16 state tail-biting error control decoder using the maximum likelihood Viterbi algorithm.
40G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-40G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
40G I.3 BCH Encoder/Decoder for ITU G.975.1
The IPrium-40G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward err…
TC1770 is a IoT-optimized turbo decoder Core compliant with LTE Cat-0 / Cat-M (release 12 and release 13).
LTE Channel Estimation IP core
hellaPHY® CE is the industry’s most LTE channel estimation IP core.
The Core can reach payload bitrates up to 2.5 Gbits/s ( equivalent baud rates > 600Mbaud).
10G I.3 BCH Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward err…
LDPC CCSDS (8160, 7136) Encoder and Decoder
The IPrium-CCSDS-LDPC-8160-7136-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algor…
The IPrium-RS-Codec IP Core implements Reed-Solomon forward error correction algorithm.
ASIC IP-core for high-throughput decoding of DVB-S2/S2X, and DVB-RCS/RCS2
Very high throughput (several Gbps) decoder that can be configured on-the-fly as: DVB-S2/S2X LDPC decoder or as Six independent D…
TC1600 is ideally suited for applications requiring small to medium block sizes in order to reduce latency and offer a high physi…
TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for FPGAs.
IEEE 802.16 WiMAX High Speed 8 State Turbo Decoder
This is a high speed IEEE 802.16 WiMAX 8 state duobinary turbo decoder with four parallel MAP decoders.