1024 State 3GPP2 Viterbi Decoder
The VA10V is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm.
- Channel Coding
- Now
- 3GPP2 C.S0098–200–0 Version…
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
1024 State 3GPP2 Viterbi Decoder
The VA10V is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm.
10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
CCSDS (8160,7136) LDPC Decoder
The LCD01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control decoder.
CCSDS (8160,7136) LDPC Encoder
The LCE01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control encoder.
Aurora-like 8b/10b @3Gbps for ALTERA Devices
REFLEX CES introduces the industry’s first release of its Aurora-‐like IP Core based on ALTERA FPGA enabling interoperability be…
64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder
The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8P…
DVB-RCS and IEEE 802.16 WiMAX turbo encoder
This is an 8 state DVB-RCS and IEEE 802.16 WiMAX compatible parallel concatenated turbo encoder.
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium…
TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible TETRA-TEDS error control decoder.
Very High Speed 3GPP LTE Turbo Decoder
This is a very high speed and fully compatible 3GPP LTE turbo decoder with one, two, four or eight parallel MAP decoders.
Very High Speed 3GPP LTE Turbo Encoder
This is a very high speed 8 state 3GPP LTE compatible parallel concatenated turbo encoder.
High Speed CCSDS Turbo Encoder
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder.
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications.
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords.
1KB/ECC96 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications.
512B/ECC16 Nand Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
1KB/ECC40 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm.
The TC4500 Core complies with DVB-T2 specifications.