BCH Decoder IP
The BCH decoder has four main functional blocks along with memory blocks.
Overview
The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about presence of errors in the encoded data. Brelekamp Massey's algorithm block computes error locator polynomial whose inverse of roots gives error locations. A polynomial solver in find error location unit solves this error locations polynomial and gives error locations indicated. For binary decoding the correction value will be just the flip of the error value which can be done using XOR gate only.
Key features
- BCH decoder compliant with the DVB-T2/S2 standard.
- Available for Altera/Xilinx FPGA or ASIC implementation.
- High speed design.
- BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
- Area and power optimized implementation.
- Compatible flexible and easy integrated with other modules.
Block Diagram
What’s Included?
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is BCH Decoder IP?
BCH Decoder IP is a Channel Coding IP core from T2M GmbH listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.