Vendor: T2M GmbH Category: Channel Coding

BCH Decoder IP

The BCH decoder has four main functional blocks along with memory blocks.

Overview

The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about presence of errors in the encoded data. Brelekamp Massey's algorithm block computes error locator polynomial whose inverse of roots gives error locations. A polynomial solver in find error location unit solves this error locations polynomial and gives error locations indicated. For binary decoding the correction value will be just the flip of the error value which can be done using XOR gate only.

Key features

  • BCH decoder compliant with the DVB-T2/S2 standard.
  • Available for Altera/Xilinx FPGA or ASIC implementation.
  • High speed design.
  • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
  • Area and power optimized implementation.
  • Compatible flexible and easy integrated with other modules.

Block Diagram

BCH Decoder IP block diagram

What’s Included?

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation

Specifications

Identity

Part Number
BCH Decoder IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Channel Coding IP core

Three Design Aspects you shouldn't miss while building an NB-IoT Protocol Stack

It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.

Frequently asked questions about Channel Coding IP cores

What is BCH Decoder IP?

BCH Decoder IP is a Channel Coding IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP