5G Polar Decoder
- Channel Coding
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
5G Polar Decoder
4G/5G Dual Mode Cell Search
LTE Turbo Decoder
LTE Viterbi Decoder
Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
ION 64b66b IP (64b/66b High-speed Serial Interface)
High-speed serial interface achieved using a lightweight protocol ION 64b66b is an IP for high-speed serial interface targeting a…
ION 8b10b IP (8b/10b High-speed Serial Interface)
High-speed serial interface achieved using a lightweight protocol ION 8b10b is a high-speed serial interface targeting applicatio…
In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…
In the DVB-T2 transmission, the Physical Layer Pipes (PLPs) carries the MPEG-2 Transport Streams (TSs).
The K-best decoder is part of the MIMO decoder.
ISDB-S3-LDPC-BCH Decoder
Adaptive Interactive detection- Per-Survivor Processing
1: CPM Modulator/ Demodulator Data Rate 200kbps to 10 Mbps in steps of 100Kbps Modulation Index Programmable up to 0.5 Baseband F…
The eMMC LDPC Encoder/Decoder is an flash reliability solution engineered to maximize flash endurance and retention.
The SCE02C is a very high speed 4 state CCSDS compatible serial concatenated convolutional code (SCCC) encoder with frame marker,…
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
The RTL is configurable for number of message bits that need ECC protection.
Zero latency, asynchronous, low power , low gate count FireCode FEC.
BCH code statistics for different `$mm` `$tt` Zero latency, low gate count, low power, asynchronous BCH Code based Error Correcti…
Reed Solomon Error Correcting Code ECC
RS Code Statistics for different values of `$mm` `$tt` Zero latency, low gate count, low power, asynchronous Reed Solomon Code ba…
Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Erasure code for RAID FEC: The whole operation of e…