What is CCSDS turbo encoder with sync marker, pseudo randomiser and input memory?
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.
Vendor:
Small World Communications
Category:
Channel Coding
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser a…
Overview
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser and input memory.
Key features
- 16 state CCSDS compatible turbo encoder
- Rate 1/2, 1/3, 1/4 and 1/6
- Interleaver sizes from 1784 to 16056 bits in multiples of 1784
- Includes sync marker, optional pseudo-randomiser and ping-pong input memory
- Up to 706 MHz internal clock
- Up to 346 Mbit/s encoding speed
- Serial continuous encoded data out
- 254 or 216 6-input LUTs with 1 or 2 18 kB RAMB18s
- Asynchronous logic free design
- Available as EDIF and VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.
Block Diagram
PCE04CH block diagram
What’s Included?
- All Licenses
- EDIF Virtex-II, Spartan-3, Virtex-4 Core
- VHDL Virtex-5, Spartan-6, Virtex-6, 7-Series, UltraScale, UltraScale+ Core
- Test vector generator
- ASIC License
- VHDL ASIC Core
Specifications
Identity
Part Number
PCE04CH
Vendor
Small World Communications
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Australia
Frequently asked questions about Channel Coding IP cores
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.