LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…
- Channel Coding
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
Nand Flash write cycles are limited.
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3a…
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.
The VK-402 searches only within a fixed number of lattice points, where the number of considered lattice points decreases as we d…
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding.
configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction.
Configurable Reed Solomon Encoder
A fully configurable Reed Solomon Encoder compliant with the requirements of nearly all modern standards that use Reed-Solomon er…
Configurable Reed Solomon Decoder
configurable Reed Solomon Decoder compliant with the requirements of nearly all modern standards using Reed-Solomon error correct…
This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed opt…
This high performance, fully configurable Reed Solomon Encoder IP Core is intended for use in a wide range of applications requir…
This high performance, fully programmable Reed Solomon Decoder IP Core is intended for use in a wide range of applications requir…
High-Speed Turbo Product Code decoder
TC3404 is a 2D TPC decoder that is optimised for high-speed.
Industry reference DVB-RCS turbo decoder
TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems.
These cores implement a Bose-Chaudhuri-Hocquenghem (BCH) error correction code configured to process a k-bit codeword, providing …
5G LDPC Decoder