Vendor: Small World Communications Category: Channel Coding

CCSDS turbo decoder with sync marker synchroniser, descrambler and input memory

This is a CCSDS compatible 16 state error control turbo decoder with optional synchronisation, optional descrambling and input me…

Contact Provider Request Datasheet

Overview

This is a CCSDS compatible 16 state error control turbo decoder with optional synchronisation, optional descrambling and input memory. The PCD04CH offers unparalleled speed, performance, low complexity and features compared to other available decoder cores.

Key features

  • 16 state CCSDS compatible
  • Rate 1/2, 1/3, 1/4 or 1/6
  • Interleaver sizes from 1784 to 16056 bits
  • Includes optional automatic synchronisation to non-inverted or inverted sync marker, optional descrambler and ping-pong input memory
  • Up to 343 MHz internal clock (log-MAP)
  • Up to 33.3 Mbit/s with 5 decoder iterations
  • 6-bit signed magnitude input data
  • Log-MAP or max-log-MAP constituent decoder algorithms
  • Up to 32 iterations in 1/2 iteration steps
  • Power efficient early stopping
  • Optional scaling and limiting of extrinsic information
  • Full estimated channel error output
  • Free simulation software
  • Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.

Block Diagram

PCD04CH block diagram

What’s Included?

  • Xilinx VHDL core
  • Test vector generator software

Specifications

Identity

Part Number
PCD04CH
Vendor
Small World Communications
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Small World Communications

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is CCSDS turbo decoder with sync marker synchroniser, descrambler and input memory?

CCSDS turbo decoder with sync marker synchroniser, descrambler and input memory is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP