Overview
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) HomePlug 1.0.1 Frame Control (FC) data, B) HomePlug AV2 Frame Control data, and C) HomePlug AV2 Payload data. This IP implements the HomePlug AV2 payload data stream. The design includes a CRC, a Scrambler, a Turbo Convolutional Encoder, and an Interleaver.
On the receiver side, The AV2 Payload Data Decoder consists of a Channel De-interleaved followed by a Turbo Convolutional Decoder, a De-scrambler, and a CRC removal unit to recover the AV2 Payload data.
Learn more about Channel Coding IP core
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