Vendor: Small World Communications Category: Channel Coding

DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder

The LCD01D is a high speed decoder for the DVB-S2/DVB-S2X low density parity check (LDPC) and Bose, Chaudhuri and Hocquenghem (BC…

Contact Provider Request Datasheet

Overview

The LCD01D is a high speed decoder for the DVB-S2/DVB-S2X low density parity check (LDPC) and Bose, Chaudhuri and Hocquenghem (BCH) code standard. All modulation and coding combinations are supported.

Key features

  • Digital Video Broadcasting Second Generation (DVB-S2) and Extensions (DVB-S2X) compatible
  • Nominal code rates from 1/5 to 9/10
  • Data lengths from 2512 to 58192 bits
  • Optional ?/2 BPSK SF2, ?/2 BPSK, QPSK, 8PSK, 8APSK, 16APSK, 32APSK, 64APSK, 128APSK and 256APSK demapping and deinterleaving with 11-bit inphase and quadrature two's complement input
  • Optional interleaved or deinterleaved 8-bit log-likelihood-ratio (LLR) input
  • Includes ping-pong input and output memories, BCH decoder and optional descrambler
  • Up to 323 MHz internal clock
  • Up to 290 Mbit/s with 30 decoder iterations
  • Up to 256 iterations
  • Programmable signal points
  • Scaled min-sum modified Gauss-Seidel LDPC decoding algorithm
  • Optional power efficient early stopping
  • LDPC parity check and BCH error location polynomial degree output
  • ~42,000 LUTs and 287 RAMB18s for Xilinx Virtex-5, Virtex-6, 7-Series, UltraScale and UltraScale+ FPGAs. ~53,000 ALUTs and 436 M10Ks for Altera Cyclone V.
  • Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.
  • Free simulation software

Block Diagram

LCD01D block diagram

What’s Included?

  • All Licenses
    • Xilinx VHDL Core
    • Test vector generator
  • ASIC License
    • VHDL ASIC Core

Specifications

Identity

Part Number
LCD01D
Vendor
Small World Communications
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Small World Communications

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder?

DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP