Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data tran…
- Channel Coding
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data tran…
The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …
25G IEEE 802.3by Reed-Solomon Forward Error Correction
Xilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise …
Narrow band - IoT Release-14 UE PHY. (L1) IP
This NB-IoT PHY.
The 8b10b line code is widely used to achieve DC-balance and bounded disparity when transmitting serial data over a medium.
Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolu…
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Reed-Solomon codes are used to perform Forward Error Correction.
Convolutional encoding is a process of adding redundancy to a signal stream.
50G IEEE 802.3 Reed-Solomon Forward Error Correction
Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications.
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) subl…
IEEE 802.3bj Reed-Solomon Forward Error Correction
Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise…
The Reed-Solomon Forward Error Correction (RS-FEC) IP Solution implements the RS-FEC sublayer specified in IEEE 802.3by/D3.1.
The Forward Error Correction (FEC) IP core is designed to comply with the Clause 74 (FEC sublayer for 10GBASE-R, 40GBASE-R, and 1…
hellaPHY™ RSTD IP core addresses new FCC E911 indoor location accuracy requirements, and opens the door for low-cost IoT wireless…
TC1620 is a high performance turbo decdoer Core compliant with DVB-RCS2 specifications.
Gigabit-range, low complexity LDPC decoder
TC4902 is ideally suited for applications requiring a very efficient throughput/area ratio, while not sacrificing SNR performance.
Error Correction Checking (ECC) Core
The Xilinx LogiCORE™ IP ECC core is ideal for robust data transmission with error correction and checking capabilities.
Xilinx provides a generic forward error correction (FEC) engine to generate and insert a SMPTE ST2022 compliant video over IP FEC…