Vendor: Xilinx, Inc. Category: Channel Coding

50G IEEE 802.3 Reed-Solomon Forward Error Correction

Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications.

Overview

Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the 25G/50G Ethernet Consortium Schedule 3 specification and connects seamlessly to the Xilinx soft 50G Ethernet Subsystem IP on Virtex® UltraScale™, Virtex UltraScale+™, Kintex® UltraScale+, and Zynq® UltraScale+ devices.

Key features

  • Low latency
  • Accessible as an integrated feature in the 50G Ethernet Subsystem
  • Configuration and status bus
  • Selectable AXI4-Lite interface for status output
  • ECC RAM option

Specifications

Identity

Part Number
EF-DI-50G-RS-FEC
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

Learn more about Channel Coding IP core

Designing with Virtex-5 Embedded Tri-Mode Ethernet MACs

In this article, we’ll review the feature set of Ethernet MAC blocks in Virtex-5 devices. We’ll also describe the differences between Virtex-5 and Virtex-4 FX Ethernet MACs, illustrate some potential applications, and describe how to use standard Xilinx tools to integrate an Ethernet MAC into your design.

Frequently asked questions about Channel Coding IP cores

What is 50G IEEE 802.3 Reed-Solomon Forward Error Correction?

50G IEEE 802.3 Reed-Solomon Forward Error Correction is a Channel Coding IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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