Overview
Reed-Solomon codes are used to perform Forward Error Correction. FEC encoders introduce redundancy in data before it is transmitted. The redundant data (check symbols) are transmitted along with the original data through the channel. A Reed-Solomon decoder at the receiver is used to recover any corrupted data. This type of error correction is widely used in data communications applications such as hard disk and media storage (CD) systems, Digital Video Broadcast (DVB) and Optical Carriers (e.g. OC-192).
The codes are represented by the format RS(n,k) where n is the total number of s-bit wide symbols, and k is the number of s-bit wide information (data) symbols in a codeword. The Reed-Solomon Decoder performs detection and correction of encoded data available at the receiver after demodulation. The RS encoded data is then processed to determine whether any errors have occurred during transmission. Once the number of errors is determined, the decoder decides if they are within the range of correction. After determining this, the decoder corrects the errors in the received data
Learn more about Channel Coding IP core
Lattice Prompt pairs with AI agentic tools developers already use, combining them with Lattice design tools, knowledge base, and documentation to turn natural language inputs into validated responses, dramatically accelerating FPGA development while optimizing design performance and capability.
First announced on May 4, 2026, the acquisition creates the industry's most complete secure management and control platform.
The acquisition brings together Lattice’s industry-leading low power FPGAs with AMI’s industry‑leading platform firmware and infrastructure manageability solutions for cloud and AI to create a complete portfolio of secure management and control solutions.
The collaboration demonstrates a real-time AI sensor fusion architecture that integrates TI mmWave radar and camera sensors using NVIDIA Holoscan Sensor Bridge running on Lattice’s low power FPGA. The FPGA acts as a companion chip delivering synchronized sensor data directly into GPU-accessible memory to enable low-latency and robust perception for robotics and industrial edge AI applications.
Sets new standard for secure control FPGAs with full CNSA 2.0-compliant post-quantum cryptography, crypto-agility, and hardware Root of Trust for next-generation infrastructure
Lattice Semiconductor today announced that the company expanded its small FPGA portfolio with new, high I/O density options in the Lattice Certus™-NX FPGA and Lattice MachXO5™-NX FPGA device families.
