The 3GPP LTE Channel Decoder provides a high-performance, optimized decode function for the Uplink Shared Channel (UL-SCH), as de…
- Channel Coding
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The 3GPP LTE Channel Decoder provides a high-performance, optimized decode function for the Uplink Shared Channel (UL-SCH), as de…
IEEE 802.15.3c Irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder
IEEE802.15.3c irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder.
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder, implemented with Continuous bits’ LDPC-decoder architecture.
Cascaded Integrator Comb (CIC) Compiler
The Cascaded Integrator Comb (CIC) Filter, or Hogenauerfilter, is a multiplier less filter architecture that is extremely importa…
The Reed-Solomon Encoder LogiCORE™ module is a high speed, compact design that implements many different Reed-Solomon coding stan…
Reed-Solomon Encoder and Decoder are commonly used in data transmission and storage applications, such as broadcast equipment, wi…
Floating Point FFT/IFFT IP Core
The Floating Point FFT IP Core (FpFft) is the most versatile available in the industry.
The Finite Impulse Response (FIR) Filter is one of the most ubiquitous and fundamental building blocks in DSP systems.
The multiplier operation is essential and abundant in DSP Applications.
The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division.
The extended dynamic range and precision offered by floating-point arithmetic is quickly becoming a requirement in numerous signa…
IP-ALFFT soft core is the unit to perform the Fast Fourier Transform (FFT).
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
The flip-flop logic is designed to be used with Platform Studio to perform simple logical operations.
The Bus Split operation is designed to be used with Platform Studio to split a bus into smaller buses.
The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based D…
UMTS/3GPP Turbo Convolutional Encoder
This version of the Turbo Convolutional encoder is designed to meet the 3GPP specification.
The Interleaver/De-interleaver LogiCORE™ module is a high-speed, compact design that is fully synchronous, using a single clock.