CMMB LDPC decoder
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder, implemented with Continuous bits’ LDPC-decoder architecture.
Overview
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder, implemented with Continuous bits’ innovative LDPC-decoder architecture. The implementation provides high data-rates, low power consumption, high silicon utilization, and reduced gate count, with low error rates.
Key features
- 1/2 and 3/4 code rates supported
- One clock synchronous design; registered inputs and outputs; global asynchronous reset
- Portable to all FPGA and ASIC technology
- FPGA proven, maximal clock frequency on Altera Stratix and Xilinx Virtex is over 100 MHz
- Internal double buffer for continuous decoding with maximal efficiency
- On-the-fly configuration of the maximal number of iterations
- Continuous monitoring of convergence enables early stops the iterations when a codeword is found
- Available as VHDL and Verilog codes
- Low power design.
Specifications
Identity
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Provider
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Frequently asked questions about Channel Coding IP cores
What is CMMB LDPC decoder?
CMMB LDPC decoder is a Channel Coding IP core from Continuous-bits Ltd. listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.