The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division.
- Arithmetic Units
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division.
The extended dynamic range and precision offered by floating-point arithmetic is quickly becoming a requirement in numerous signa…
The CMS0014 DVB-S2 (A)PSK Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S2 and DVB-S2X forward link …
IP-ALFFT soft core is the unit to perform the Fast Fourier Transform (FFT).
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
The flip-flop logic is designed to be used with Platform Studio to perform simple logical operations.
The Bus Split operation is designed to be used with Platform Studio to split a bus into smaller buses.
The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based D…
UMTS/3GPP Turbo Convolutional Encoder
This version of the Turbo Convolutional encoder is designed to meet the 3GPP specification.
The Interleaver/De-interleaver LogiCORE™ module is a high-speed, compact design that is fully synchronous, using a single clock.
The Xilinx LogiCORE™ CORDIC IP implements a generalized coordinate rotational digital computer (CORDIC) algorithm, initially deve…
The Xilinx® LogiCORE™ IP Convolutional Encoder core can be used in a wide variety of error correcting applications and is typical…
The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers…
The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations.
Aliathon’s 2.5Gbps GFP-T Encoder Core provides a flexible, resource-efficient, high-density programmable logic based solution for…
NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications.
Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fa…
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …