Overview
The Reed-Solomon Encoder LogiCORE™ module is a high speed, compact design that implements many different Reed-Solomon coding standards including G.709, DVB, ATSC, IEES, ITU-T J.83 and CCSDS. The core is fully synchronous, using a single clock, and supports continuous output data with no gap between code blocks. The core is parameterizable, allowing designers to control the symbol width and the code block length. This module supports shortened codes and any primitive field polynomial for a given symbol width. The core supports a user-configured generator polynomial.
Learn more about Channel Coding IP core
This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.
We describe our SoC implementation of a baseband subsystem for a high performance 4G terminal. Our architecture, called FAUST, is based on distributed synchronization and asynchronous communication. We highlight how we have actually implemented these two
Satellite modems structure Internet access
DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.
In this paper, a typical research case will be described on how to extend an existing SoC architecture of baseband processor on 3G terminal to the player on network multimedia compressed with MPEG-4, especially on how to build an effectively multi-layer a
