Overview
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception. Compatible with many common standards such as DVB, 3GPP2, IEEE802.16, HiperLAN, Intelsat IESS-308/309, the Viterbi Decoder LogiCORE™ IP, along with other forward error correction cores from Xilinx offers highly-flexible concatenated codecs. The Viterbi Decoder LogiCORE IP consists of two basic architectures: a fully parallel implementation which gives fast data throughput and a serial implementation which occupies a small area. The core also has a puncturing option, giving a large range of transmission rates and reducing the bandwidth requirement on the channel. Puncturing can also be carried out externally to the decoder and the erasure pins in the erasure bus ERASE can be asserted to indicate the presence of null-symbols.
Learn more about Channel Coding IP core
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
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AMD (NASDAQ: AMD) and Xilinx, Inc. (NASDAQ: XLNX) today released the following statement related to the status of global regulatory approvals for AMD’s proposed acquisition of Xilinx.
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