Tutorial: Floating-point arithmetic on FPGAs
This article explains the basics of floating-point arithmetic, how floating-point units (FPUs) work, and how to use FPGAs for easy, low-cost floating-point processing.
Vendor:
Xilinx, Inc.
Category:
Arithmetic Units
Divider
The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division.
Overview
The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division. The integer division can be implemented using Radix-2 non-restoring division, or High Radix division with prescaling division algorithms.
The Radix-2 algorithm is implemented using the logic fabric and provides up to 32 bits operands along with the ability to control the degree of parallelism used in the algorithm. By controlling the parallelism of the implementation, users can make trade-offs between performance and resources. The High-Radix division with prescaling algorithm is designed to exploit the DSP48 (multiply-add) capability to provide an efficient, low-latency implementation for up to 54 bits operands. The Radix-2 algorithm is suitable for implementing smaller operand division, and High Radix division, better suited for implementing large (above about 25 bits wide) operands.
The Radix-2 algorithm is implemented using the logic fabric and provides up to 32 bits operands along with the ability to control the degree of parallelism used in the algorithm. By controlling the parallelism of the implementation, users can make trade-offs between performance and resources. The High-Radix division with prescaling algorithm is designed to exploit the DSP48 (multiply-add) capability to provide an efficient, low-latency implementation for up to 54 bits operands. The Radix-2 algorithm is suitable for implementing smaller operand division, and High Radix division, better suited for implementing large (above about 25 bits wide) operands.
Key features
- AXI4-Stream-compliant interfaces
- Integer division with operands of up to 64 bits wide
- Offers Radix-2, LUTMult and High Radix implementation algorithms to allow choice of resource and latency trade-offs
- Optional operand widths, synchronous controls, and selectable latency
- Optional divide by zero detection
- C model for system-level simulation (bit accurate with core except for division by zero)
Specifications
Identity
Part Number
Divider
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Arithmetic Units IP core
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Frequently asked questions about Arithmetic Unit IP cores
What is Divider?
Divider is a Arithmetic Units IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Arithmetic Units?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.