Vendor: Xilinx, Inc. Category: Channel Coding

UMTS/3GPP Turbo Convolutional Encoder

This version of the Turbo Convolutional encoder is designed to meet the 3GPP specification.

Overview

This version of the Turbo Convolutional encoder is designed to meet the 3GPP specification. In addition, a user generated external interleaver can be used and code rates of 1/5 is supported to provide additional flexibility.

Key features

  • Implements the 3GPP/UMTS specification
  • Core contains the full 3GPP interleaver
  • Full 3GPP block size range supported: 40 - 5114
  • Up to 16 simultaneous data channels
  • Double-buffered symbol memory for maximum throughput
  • Rate 1/3 parity outputs for 3GPP and optional outputs for rate 1/5 for additional error correction capability
  • Flexible interfacing by means of optional control signals
  • Support for External RAM
  • External address generator option enables interfacing to customer-designed interleaver

Specifications

Identity

Part Number
EF-DI-TCCENC-UMTS-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

Learn more about Channel Coding IP core

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Frequently asked questions about Channel Coding IP cores

What is UMTS/3GPP Turbo Convolutional Encoder?

UMTS/3GPP Turbo Convolutional Encoder is a Channel Coding IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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