Tutorial: Floating-point arithmetic on FPGAs
This article explains the basics of floating-point arithmetic, how floating-point units (FPUs) work, and how to use FPGAs for easy, low-cost floating-point processing.
Vendor:
Xilinx, Inc.
Category:
Arithmetic Units
Multiplier
The multiplier operation is essential and abundant in DSP Applications.
Overview
The multiplier operation is essential and abundant in DSP Applications. Achieving maximum implementation efficiency and clock performance is therefore critical to DSP systems and frequently presents a significant challenge to hardware engineers.
The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.
This IP provides fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding implemented in the DSP48 slice. Fully pipelined implementations enable maximum clock frequency performance
The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.
This IP provides fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding implemented in the DSP48 slice. Fully pipelined implementations enable maximum clock frequency performance
Key features
- 2's complement signed/unsigned fixed point multiplier
- Parallel and fixed constant coefficient multipliers
- Supports Inputs ranging 1 to 64 bits wide and outputs ranging from 1 to 128 bits wide with any portion of the full product selectable
- Supports symmetric rounding to infinity when using the DSP Slice
- Instantaneous Resource Estimation
- Optional Clock Enable, and Synchronous Clear
- VHDL behavioral models
- Instantaneous Resource Estimation
- For use with Vivado® IP Catalog and Xilinx System Generator for DSP
Specifications
Identity
Part Number
Multiplier
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Arithmetic Units IP core
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Frequently asked questions about Arithmetic Unit IP cores
What is Multiplier?
Multiplier is a Arithmetic Units IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Arithmetic Units?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.