Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The J5 is a core cell design of an application specific signal processor which performs both Trusurround(TM) and SRS® 3-D audio v…
The NAND Flash landscape is changing and the Arasan NAND flash management technology is changing with it.
The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the sp…
Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
Revolutionary vector processor
From early Motorola and TI DSPs to modern smartphone DSPs in application processors, DSPs have been designed and optimized for in…
Crest Factor reduction block minimizes the likelihood that a transmission side Power Amplifier (PA) gets saturated while transmit…
As serial link speeds have increased, the reach achievable has become more and more limited by the lossy nature of the physical m…
Digital PID Controller Loop Algorithms for EMA
We have developed control system algorithm IP blocks to be able to control electromagnetic actuators.
Multiplexer 2x 16 to 1 - XFAB 180nm
Multiplexer 2x 16 to 1 - XFAB 180nm
Binary to One-hot coder, 6bit - XFAB 180nm
Binary to One-hot coder, 6bit - XFAB 180nm
Binary to One-hot coder, 4bit - XFAB 180nm
Binary to One-hot coder, 4bit - XFAB 180nm
RF Counter, 16b - STMicroelectronics 65nm
RF Counter, 16b - STMicroelectronics 65nm
Included with Xilinx ISE Software The BUFT-based Multiplexer Slice IP core supports buses of up to 64 bits wide and 1 to 64 input…
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.
Included with Xilinx ISE Software The BUFE-based Multiplexer Slice IP core supports buses of up to 64 bits wide and 1 to 64 input…
Vector Floating-point coprocessor based on ARM VFPv2 Instruction Set Architecture for FA626TE 32-bit RISC CPU
24-bit digital signal processor soft core.
24-bit digital signal processor soft core.
16-bit digital signal processor soft core
16-bit digital signal processor soft core.
16-bit digital signal processor soft core
16-bit digital signal processor soft core.
Customize a modem with various building blocks, e.g.