Floating Point FFT/IFFT IP Core

The Floating Point FFT IP Core (FpFft) is the most versatile available in the industry. It is designed to address the design challenges of digital signal processing in FPGA's today. It is the only floating point FFT IP Core can be tailored made to meet exact needs of your application.

By optimizing the mantissa and exponents lengths for the target technology and application, tremendous gains in dynamic range and precision can be attained ver sus the normal fixed point FFT results with a minimal impact on device size and cost.

The processing speed of the core is increased by adding butterfly structures in parallel. For ultra high performance applications, parallel data paths into and out of the module can be added to allow the system to maintain a reasonable clock rate. The speed of operation is only limited by the amount of available logic in the target device.

An FFT Development Kit provides C math modeling with bit accurate results and HDL simulation behavioral models which drastically improve simulation perfor mance.

The FpFFT is also utilized in DE's ultra-long and 2D FFT engines, producing re sults far more accurate than fixed point solutions.

The FpFFT Core is a ParaCore ArchitectTM IP Core, making configuration option specification at compile time via parameters.

• Worlds fastest and most flexible Floating Point FFT IP Core
• Ultra high performance (> 1GSPS possible)
• Custom precision, any exponent and mantissa width
• Clock speeds over 200 MHz in Virtex II Pro 
• IEEE 754 compliant
• Parametric IP core for maximum flexibility
• Available in generic HDL or targeted EDIF formats
• Full test bench supplied
• Any radix-2 or split radix lengths
• Mixed radix configurations - radix-2 x radix-3, radix-2 x radix-5, and radix-2 x radix-7
• Ultra long FFTs with external SRAM, both ZBT and DDR SRAM supported
• Naturally ordered I/O streams
• ParaCore ArchitectTM IP Core
• Massively parallel butterfly architecture
• FFT Development Kit supplied with IP