Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the …
- Single-Protocol PHY
- Silicon Proven
Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the …
The Multi-protocol SerDes (MPS) PHY is a comprehensive PAM-4 solution that provides high-performance, multi-lane capability and l…
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
The 32G SerDes PHY is a configurable IP solution capable of supporting data rates of up to 32 Gbps per lane.
5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
5G Combo Serdes for USB/PCIe, TSMC 22ULL 2.5V, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
5G Combo Serdes for USB/PCIe, TSMC 22ULL 1.8V, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
5G Combo Serdes for USB/PCIe, TSMC 12FFC, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
10G Combo Serdes for USB/PCIe/Ethernet, SMIC 14FF, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
10G Combo Serdes for USB/PCIe/Ethernet, TSMC 28HPC+, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
M31 Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
The SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data…
The 10 Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables the creation of system solutions for 10 …
Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…
Ethernet PCS IP - Integrates MAC IP to a broad range of PHY and SerDes IP
The Ethernet PCS and connectivity IP provide you with a wide range of connectivity IP that can be used to interface Cadence and t…
The LDS SATA RECORDER XV6 IP is a recorder system IP.
YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstr…
No charge paramaterizable core which utilizes the serial I/O transceivers available in the Kintex® UltraScale™, Virtex® UltraScal…