XAUI SerDes Phy IP Listing

Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the …

• Single-Protocol PHY
• Silicon Proven

The Multi-protocol SerDes (MPS) PHY is a comprehensive PAM-4 solution that provides high-performance, multi-lane capability and l…

• Multi-Protocol PHY

The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.

• Single-Protocol PHY

The 32G SerDes PHY is a configurable IP solution capable of supporting data rates of up to 32 Gbps per lane.

• Multi-Protocol PHY

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• TSMC
• 28nm
• HPC+

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• TSMC
• 22nm
• ULL

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• TSMC
• 22nm
• ULL

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• TSMC
• 12nm
• FFC

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• SMIC
• 14nm
• FF

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• TSMC
• 28nm
• HPC+

M31 Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

• TSMC
• 7nm
• N7+

The SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data…

• Multi-Protocol PHY

The 10 Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables the creation of system solutions for 10 …

• Single-Protocol PHY

Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…

• TSMC
• 40nm
• LP

The Ethernet PCS and connectivity IP provide you with a wide range of connectivity IP that can be used to interface Cadence and t…

• Single-Protocol PHY
• Silicon Proven

The LDS SATA RECORDER XV6 IP is a recorder system IP.

• SATA Controller
• Now

YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstr…

• Video Processing
• Silicon Proven

No charge paramaterizable core which utilizes the serial I/O transceivers available in the Kintex® UltraScale™, Virtex® UltraScal…

• Ethernet