Overview
No charge paramaterizable core which utilizes the serial I/O transceivers available in the Kintex® UltraScale™, Virtex® UltraScale, Virtex-7, Kintex-7, Artix®-7, Zynq®-7000, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro and Spartan®-6 to support the XAUI function.
The Xilinx 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE™ IP provides a 4-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2012. In addition, the core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2012 clause 45 management registers. The MDIO interface may be omitted to save logic, in which case a simplified management interface is provided via bit vectors.
Learn more about Ethernet IP core
The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit.
In this article, we’ll review the feature set of Ethernet MAC blocks in Virtex-5 devices. We’ll also describe the differences between Virtex-5 and Virtex-4 FX Ethernet MACs, illustrate some potential applications, and describe how to use standard Xilinx tools to integrate an Ethernet MAC into your design.
Flexible FPGA fabric, embedded multi-gigabit transceivers, and off-the-shelf IP enable robust, high performance, and high-integration serial backplane interface solutions
