Multi-Standard SerDes PHY

The SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data storage, enterprise routers, servers, industrial & test equipment, defence and aerospace etc. With seamless interoperability with available controllers it provides unique solution to customer’s system applications.

The vendor offers low power, low latency, integrated clocking and small footprint SerDes Quad PHY IP that supports one, two, four lanes per macro configuration.

• Configurable parallel data rate of 8 /10 / 16 / 20 / 32 / 40 / 64 / 80
• Input reference 5MHz to support 2.5/5/10G data rates
• Tight control over termination resistor (~50 Ohm) with on chip calibration
• Tight skew control of 1UI between lanes of the PMA
• Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
• Lowest latency
• Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
• Programmable/automatic calibration of key circuits (pre-emphasis, eye-diagram monitoring / DFE tap calibration / offset calibration)
• CDR logic for better data alignment and locking
• Support for bifurcation and quadfurcation modes
• Multi-tap Rx DFE (decision feedback equalizer)
• Programmable internal/external loopback modes between TX and RX
• SRnS (Separate Reference no Spread) support
• Includes ESD structures
• Operation across a wide temperature range (-40 C to +125 C)

• User and integration guides
• Netlist
• Timing library
• Register map
• Verilog
• IBIS-AMI models
• LEF views
• Layout Versus Schematic (LVS)
• Design Rule Check (DRC) reports
• Silicon