10G Combo Serdes for USB/PCIe/Ethernet, SMIC 14FF, N/S orientation
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
Overview
The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The Serdes IP supports data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-KR, CEI, XAUI, USXGMII, QSGMII, and SGMII. With the supports for both TX and RX equalization techniques, the Serdes IP is designed to meet the requirements for different channel conditions.
Key features
- Supports 1.25G to 10.3125Gbps data rates and compact die area
- Supports up to 25dB channel loss@ 5.15625GHz
- Supports RX loss-of-signal detection
- Supports X1, X2 and X4 lanes
- Accessible register controls allow user specific optimization of critical parameters (e.g., TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
- Supports both FOM for Link-EQ Training
- Supports robust BIST functions for mass production testing
- Support Wire-Bond and Flip-Chip packages
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 14nm | FF | — |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Ethernet IP cores
What is 10G Combo Serdes for USB/PCIe/Ethernet, SMIC 14FF, N/S orientation?
10G Combo Serdes for USB/PCIe/Ethernet, SMIC 14FF, N/S orientation is a Ethernet IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for smic.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.