Vendor: M31 Technology Corp. Category: Multi-Protocol PHY

5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.

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TSMC 28nm HPC+ View all specifications

Overview

The Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The Serdes IP supports data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-KR, CEI, XAUI, USXGMII, QSGMII, and SGMII. With the supports for both TX and RX equalization techniques, the Serdes IP is designed to meet the requirements for different channel conditions.

Key features

  • Supports 1.25G to 10.3125Gbps data rates and compact die area
  • Supports up to 25dB channel loss@ 5.15625GHz
  • Supports RX loss-of-signal detection
  • Supports X1, X2 and X4 lanes
  • Accessible register controls allow user specific optimization of critical parameters (e.g., TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Supports both FOM for Link-EQ Training
  • Supports robust BIST functions for mass production testing
  • Support Wire-Bond and Flip-Chip packages

Block Diagram

5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 28nm HPC+ —

Specifications

Identity

Part Number
5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation
Vendor
M31 Technology Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact M31 Technology Corp.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation?

5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation is a Multi-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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