Overview
The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of the data to record.
The data can be recorded in FAT32 or in RAW format. In FAT32 mode, the disks must be already formatted or can be formatted through the Ethernet link and a PC under windows or Linux (free driver).
The Ethernet link, when used, enables to download FAT32 files into your PC to process them later according user application.
The ‘Generator_Checker’ block enables to check any recording error in the data flow.This block generates a counter which is written into disks and then readback and compared in order to detect any recording error. External data goes through this block.
A User Interface on a Hyperterminal enables to configure all the recording session (recording size, file size, raid0 strip, number of disk, read directory, etc…) and enables to run a write and read performance test of the system using the ‘Generator_Checker’ block. It enables you to chek the performance of your systems, especially the disks.
Netlist and VHDL source code format is available for ease of customization. The C source code is always provided. The customization can be done by Logic Design Solutions.
Learn more about SATA Controller IP core
Many times we are not aware of very useful EDA tool options which are already available. Even if such options are very well documented, we don't look at them and try them. But some options are very useful and if you know them, it makes job of design engineer and/or verification engineer very easy. Here, I am going to talk about one very powerful and useful VSIM option of QuestaSim. It is VCDSTIM option of VSIM.
The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation.
Oftentimes, in order to save on the cost of IP, a company will select an encrypted netlist as the deliverable instead of the RTL source code. This is especially common among companies looking to develop in FPGA devices where they can often get the necessary IP from their FPGA vendor.
To support High Definition Television (HDTV) application, the System on Chip (SoC) presented in this paper has to support multiple and concurrent internal processes. Most of these operations read data from memory, process them and store the resulting data into memory. Each functional unit of the system is responsible for a specific data processing, but all the data are stored in the same shared external memories.
Eric Esteve
Eric Esteve
