USB 2.0 OTG PHY IP, OTG, UMC 0.11um HS/AE process
USB 2.0 OTG PHY, UMC 0.11um HS AL Logic process.
- UMC
- 110nm
- HS
USB 2.0 OTG PHY IP, OTG, UMC 0.11um HS/AE process
USB 2.0 OTG PHY, UMC 0.11um HS AL Logic process.
The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.
The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s…
The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface.
The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication ma…
The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…
USB 2.0 OTG Dual Role Device (DRD) Controller
The Arasan USB 2.0 OTG DRD IP Core is compliant with the OTG Supplement Rev.
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
The Synopsys USB 2.0 Controllers support Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation based on U…
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
GLOBALFOUNDRIES 28nm USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
LTTS USB 2.0 OTG controller are designed for compliance with USB2.0 specification Revision 2.0 and all associated ECN’s and USB O…
USB 3.0/3.1/3.2/SSIC Verification IP
USB 3.0/3.1/3.2 Verification IP provides a smart way to verify the USB 3.0/3.1/3.2 component of a SOC or a ASIC.