Simplifying Multi-Domain Voltage-Control Verification with Synopsys AVSBus 2.0 VIP
Learn how AVSBus 2.0 VIP validates power delivery in AI and data center SoCs.
Vendor:
Synopsys, Inc.
Category:
USB
USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
Overview
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. The digital controllers provide: the lowest gate count; power management optimized with dual power rails; and a ULPI interface for discrete PHYs and UTMI/UTMI+ interface for integrated PHYs. This comprehensive solution includes the USB 2.0 LPM-HSIC, OTG, Host and Device Controllers.
The USB 2.0 IP is the most certified IP solution in the industry. With thousands of design wins and billions of silicon-proven units shipped, the vendor's complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
The vendor optimized the USB 2.0 Controllers for low power, small area and ease-of-integration, such as is required in Internet of Things (IoT) applications.
Key features
- Configuration options to maximize performance and minimize CPU interrupts
- Flexible parameters enable easy integration into low and high-latency systems
- Transfer- or transaction-based processing of USB data based on system requirements
- Configurable data buffering options to fine-tune performance/ area trade-offs
- Buffer and descriptor pre-fetching maximizes host throughput
- Firmware-selectable endpoint configurations enable post-silicon application changes and the flexibility of one-chip design for multiple applications
- Quality IP is tested through extensive Constrained Random Verification
- AMBA™ High-Performance Bus (AHB) interface enables rapid integration into ARM-based designs
- UTMI+ Level 3 enables rapid integration with compatible PHYs
- Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low- Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
- The USB 2.0 HS OTG Controller operates as either peripheral or host
- The Hi-Speed USB EHCI Host Controller is also available
Block Diagram
dwc_usb_2_0_hs_otg_subsystem-ahb block diagram
Specifications
Identity
Part Number
dwc_usb_2_0_hs_otg_subsystem-ahb
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about USB IP core
Synopsys Joins Arm Total Design for Physical AI to Advance Autonomous Systems
Learn how Synopsys and Arm Total Design help accelerate Physical AI systems with pre-validated IP, virtual development, and system-level design.
Synopsys Advances Agentic AI Chip Design with AMD and Microsoft
Introduces Industry's First Autonomous EDA Workflows on Microsoft Discovery to Accelerate Engineering from Specification to Silicon
Synopsys and Intel Foundry Fast-Track Customer Readiness from Silicon to Systems on Intel 14A
Certified AI-powered EDA flows, integrated multiphysics analysis, and broad IP portfolio accelerate Angstrom-scale AI and multi-die designs
Synopsys Showcases Comprehensive Autonomous Engineering Workflows from Silicon to Systems, Developed with NVIDIA Technology
Synopsys unveils a fully autonomous long-running design verification agent that orchestrates the entire chip verification cycle delivering up to 50X faster time-to-validated RTL while achieving 20% additional coverage improvement
World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
Synopsys delivers standards-compliant 112G PHY IP for linear optics, helping reduce AI interconnect power, latency, and heat.
Frequently asked questions about USB IP cores
What is USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)?
USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only) is a USB IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.