USB 2.0 OTG Dual Role Device (DRD) Controller

The Arasan USB 2.0 OTG DRD IP Core is compliant with the OTG Supplement Rev. 1.0a. The USB 2.0 OTG DRD core supports the Host Controller, Device Controller, and OTG functionality. It supports Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) (USB 2.0 Speeds) specifications. AHB interface is available to provide a high-speed connection to the USB interface.

Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) are managed by the SRP/ HNP Control Logic. SRP allows a Peripheral (B-device) to request a Host (A-device) to turn on Vbus to start a session, while HNP allows two connected dual-role devices to change roles and eliminates the need for the user to switch cable connections. The Vbus Control Circuit supports the generation of data-line pulsing and Vbus pulsing methods when initiating the SRP as a B-device, the detection of both pulsing methods when acting as an A-device, and the sourcing of a minimum of 8 mA on Vbus. The Vbus Control Circuit also handles the pull-up and pull-down connections to D+ during host/device role switching. The SRP/HNP Logic and Vbus Control Circuit control the operating mode of a USB port as either a host or a peripheral. The Arasan USB 2.0 OTG port requires an external USB 2.0 transceiver with a standard UTMI interface.

• Compliant with OTG Supplement Rev. 1.0a
• USB 2.0 Compliant
• Supports 480 Mbit/s (HS), 12 Mbit/s (FS), and 1.5 Mbit/s (LS)
• Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
• Supports data-line pulsing and Vbus pulsing as A-device or B-device
• High/Full speed support using 8/16-bit UTMI/ULPI interface
• USB transaction protocols are handled by hardware
• Minimum 8 mA Vbus and over 500 ma sourcing to peripherals with 5 V external power supply
• Suspend/resume support for power management
• 32-bit AHB bus Interface
• Master DMA implementation for each endpoint
• UTMI+ PHY Interface Clock: 30/60 MHz
• Configurable up to 15 Tx and Rx endpoints
• Configuration options: Bulk, Control, Isochronous, Interrupt
• Configurable dual port RAM shared between endpoints

• RMM-compliant synthesizable RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents
• Simulation scripts