Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Ethernet 1G/10G flexiMAC MACO Core
The LatticeSCM Ethernet flexiMAC™ MACO™ IP core is a flexible packet framer and parser that can implement Layer2 (data link layer…
The Divider IP core is a one-clock divider which completes one integer division every clock.
The latest trend in portable computer power management is Switchable Graphics.
Lattice DFE (Digital Front End) demo provides a digital solution consisting of CPRI (Common Public Radio Interface), DUC (Digital…
The Deinterlacer IP core converts input video stream from interlaced format into progressive format and uses bob, intra and inter…
The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory contr…
The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3…
DDR/DDR2 SDRAM Controller MACO Core
The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that in…
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz.
DDR SDRAM Controller - Non-Pipelined
This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined versio…
As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…
As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…
Crest factor reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such as those used …
Convolutional encoding is a process of adding redundancy to a signal stream.
Color Space Converters (CSC) are used in video and image display systems including televisions, computer monitors, color printers…
CMOS to MIPI CSI-2 Interface Bridge IP
Many traditional image sensors have a CMOS interface.
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size.
The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described…
The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
The GbE PCS Intellectual Property (IP) Core targets the programmable array section of the ORCA ORT42G5 FPSC and provides the PCS …