PCIe Gen 6 Phy
- Multi-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PCIe Gen 6 Phy
Image Codec/Encoder/Decoder - ISO/IEC 10918-1 JPEG standard
Image Codec/Encoder/Decoder - ISO/IEC 10918-1 JPEG standard
1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF s…
A 2Gbps LVDS Tranceiver in TSMC 28nm This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power …
1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with ultra low-cap/low-leakage 36V+ ESD…
1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
High-Voltage Single-Ended / Differential I/O Macro in TSMC 16FFC This library is a high-voltage GPIO I/O Macro in TSMC 16nm.
A 2Gbps SLVS Tranceiver in TSMC 28nm This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs…
0.9V/2.5V I/O Library in TSMC 55nm
A 0.9V/2.5V In-Line I/O Library in TSMC 55LP.
1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
A Fail-Safe Digital I/O Library.
1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells an…
ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
A Wirebond and FlipChip compatible
Wirebond Digital and Analog Library in TSMC 65nm
A mixed Digital and Analog Library, compatible with I2C and I3C Protocols.
5V FSGPIO, 5V GPIO, 5V GPI, 5V ODIOy in DB HiTek 130nm
A Flip-Chip compatible I/O Library in Dongbu HiTek 130nm with 5V FSGPIO, 5V GPIO, 5V GPI, I2C-compliant ODIO and associated ESD.
I/O Library in TSMC 130nm 5V Gen3 BCD
A TSMC 130nm Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O.
Ultra-low leakage I/O Library in TSMC 22nm
A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associ…
1.8V/3.3V Switchable GPIO in TSMC 28nm
A TSMC 28nm Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, with Specialized RF Wirebond Cells for LNAs.
2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
A 2Gbps differential transceiver.
Special Purpose Low (Statistical) offset Operation Amplifier
The WEAOPSPLO18PI18RO12M22G is a special purpose low offset buffer for bias generator that provides a buffered ouput for the Temp…